Iterative decoding algorithms for low-density parity-check codes allows a high degree of parallelism in processing, favoring the design of high throughput architectures of the decoder. However, routing congestion and memory collision might limit a practical exploitation of the inherent parallelism a decoding algorithm. In order to solve this problem, codes are designed with a block structure (having blocks of size P) that naturally fit with the vectorization of the decoder architecture, thus guaranteeing a collision-free parallelism of P.
Multi-level low-density parity-check codes have much better performance than binary low-density parity-check codes. However, they also have much greater hardware complexity than binary low-density parity-check code decoders, which leads to prohibitively large size and power consumption in hardware.
Consequently, it would be advantageous if an apparatus existed that is suitable for multi-level low-density parity-check code decoding with reduced complexity and power consumption.